1. Field of the Invention
The present invention relates to a memory control apparatus, and a method for controlling the same. In particular, the present invention relates to a memory control apparatus and a method for controlling the same which achieve efficient data transfer with a smaller number of buffers.
2. Description of the Related Art
FIG. 1 illustrates the structure of a known memory control apparatus 1.
In FIG. 1, the memory control apparatus 1 includes three input ports, input ports 111, 112, and 113, and three output ports, output ports 141, 142, and 143. The memory control apparatus 1 outputs data that is inputted thereto via each of the input ports 111 to 113 via one of the output ports 141 to 143 through a memory control section 12 and a signal switch section 13.
Specifically, with reference to FIG. 1, data that has been inputted to the memory control section 12 via the input port 111 is stored in a buffer 221, selected by a write control section 211. Then, the data stored in the buffer 2211 is outputted, as output data, via the output port 141 selected by a read control section 231 by way of the signal switch section 13.
The signal switch section 13 is a device for routing a signal from an arbitrary one of buffers 2211, 2212, 2221, 2222, 2231, and 2232 to an arbitrary one of the output ports 141 to 143.
At this time, upon completion of the writing of the data into the buffer 2211, the write control section 211 selects the buffer 2212 as a buffer to which next data is to be written. As a result, the write control section 211 is able to write the next data from the input port 111 into the buffer 2212 instantly, even if reading of the data from the buffer 2211 is not completed by the read control section 231. Note, however, that in the case where the reading of the data from the buffer 2211 is not completed when the writing of the data into the buffer 2212 is complete, the write control section 211 is prohibited from writing next data into the buffer 2211.
In FIG. 1, a set of a write control section 212, the buffers 2221 and 2222, and a read control section 232, and a set of a write control section 213, the buffers 2231 and 2232, and a read control section 233, have the same structure and operate in the same manner as the set of the write control section 211, the buffers 2211 and 2212, and the read control section 231. Therefore, descriptions thereof are omitted.
Next, with reference to a timing diagram of FIG. 2, operations of the buffers 2211 to 2232 as illustrated in FIG. 1 will now be described below.
In FIG. 2, rectangles represent that the corresponding buffer is in use, and concerning the operation of each of the buffers 2211 to 2232, a data writing process (Write) and a data reading process (Read) are distinguished from each other in representation. A horizontal axis represents a time axis, and the time passes from left to right in the figure.
As illustrated in FIG. 2, while the process of writing the data into the buffer 2211 is performed, the process of writing the data is not performed in the buffer 2212, and during this time, no particular process is performed therein. Then, after the writing of the data from the input port 111 into the buffer 2211 is completed, the process of reading the data from the buffer 2211 is performed, while the process of writing data into the buffer 2212 is started.
That is, while one of the pair of the buffers 2211 and 2212 performs the writing process, the other is allowed to perform any other process than the writing process, i.e., the reading process, until the writing process in the former is completed. In other words, the writing process is not performed simultaneously in the buffers that are paired with each other. This is also true with the other pairs of buffers as illustrated in FIG. 1, i.e., the pair of the buffers 2221 and 2222 and the pair of the buffers 2231 and 2232, as shown in FIG. 2.
As described above, the memory control apparatus 1 accomplishes the data transfer by performing the writing process or the reading process while switching between the buffers 2211 and 2212, between the buffers 2221 and 2222, and between the buffers 2231 and 2232.
The present assignee has proposed a technique related to memory control (see, for example, Japanese Patent Laid-Open No. 2005-92630, hereinafter referred to as Patent Document 1).
In this previously proposed technique, the reading and writing of the data from or into the memory are controlled in accordance with an order in which access requests are processed.